SH7720 Datasheet, PDF (1004/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 27 A/D Converter
27.4.4 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit is set to 1, then starts conversion. Figure 27.5 shows the A/D
conversion timing. Table 27.3 indicates the A/D conversion time.
As indicated in figure 27.5, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 27.3.
In multi mode and scan mode, the values given in table 27.3 apply to the first conversion. In the
second and subsequent conversions the conversion the conversion time is fixed at 512 states
(fixed) when CKS1 = 1 and CKS0 = 0, 256 states (fixed) when CKS1 = 0 and CKS0 = 1, and 128
states (fixed) when CKS1 = 0 and CKS0 = 0.
*¹
Pφ
Address _*2
Write
signal
Input sampling
timing
ADF
t_D
t_SPL
t_CONV
t_D
t_SPL
t_CONV
Notes:
A/D conversion start delay
Input sampling time
A/D conversion time
1. ADCSR write cycle
2. ADCSR address
Figure 27.5 A/D Conversion Timing
Rev. 3.00 Jan. 18, 2008 Page 942 of 1458
REJ09B0033-0300