SH7720 Datasheet, PDF (1476/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
21.3.9 FIFO Control Register
(SIFCTR)
Page Revision (See Manual for Details)
701, Changed
702 _{Bit Bit Name Description}
15 TFWM2 …
14 TFWM1 • A transfer request to the transmit
13 TFWM0 ^{FIFO is issued by the TDREQ bit}
in SISTR.
• The transmit FIFO is always used
as 16 stages of the FIFO
regardless of these bit settings.
7 RFWM2 …
6 RFWM1 • A transfer request to the receive
5 RFWM0 ^{FIFO is issued by the RDREQ bit}
in SISTR.
• The receive FIFO is always used
as 16 stages of the FIFO
regardless of these bit settings.
21.4.7 Transmit and Receive
721
Procedures
(1) Transmission in Master Mode
Figure 21.9 replaced.
8
Clear the TXE bit in SICTR to 0
Set to dis
9
Set the FSE bit in SICTR to 0
Set the MSSEL bit in SISCR to 1
Set BRDV=111
and BPRS=00000 in SISCR
10
Add pulse (0→1→0)
to the TXRST in SISCR
Synchronize this LSI internal
frame with FSE=0 if restarting
transmit later.
Execute internal initialization
of the bit rate generator
if restarting transmit later.
Reset the master clock source
and baud rate in SISCR
'No' requires further setting
11
Change other No
transmit mode?
if transmission is not restarted
(No).
When returning to the same
Yes
End
transmit mode from here,
go back to No.4, FSE setting,
on this flowchart.
12
Start the setting FSE=0,
TXE=0 and other bit.
Go to "Start" on each flowchart.
Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the
TXE bit should be set to 1.
Rev. 3.00 Jan. 18, 2008 Page 1414 of 1458
REJ09B0033-0300