SH7720 Datasheet, PDF (132/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Instruction
Instruction Code Operation
Privileged
Mode
Cycles T Bit
EXTS.B Rm,Rn
0110nnnnmmmm1110 A byte in Rm is sign-extended –
→ Rn
1
–
EXTS.W Rm,Rn
0110nnnnmmmm1111 A word in Rm is sign-extended –
→ Rn
1
–
EXTU.B Rm,Rn
0110nnnnmmmm1100 A byte in Rm is zero-extended –
→ Rn
1
–
EXTU.W Rm,Rn 0110nnnnmmmm1101 A word in Rm is zero-
–
extended → Rn
1
–
MAC.L
@Rm+,
@Rn+
0000nnnnmmmm1111 Signed operation of (Rn) × –
(Rm) + MAC → MAC,
Rn + 4 → Rn, Rm + 4 → Rm
32 × 32 + 64 → 64 bits
2 (to 5)* –
MAC.W @Rm+,
@Rn+
0100nnnnmmmm1111 Signed operation of (Rn) × –
(Rm) + MAC → MAC,
Rn + 2 → Rn, Rm + 2 → Rm
16 × 16 + 64 → 64 bits
2 (to 5)* –
MUL.L
Rm,Rn
0000nnnnmmmm0111 Rn × Rm → MACL
32 × 32 → 32 bits
–
2 (to 5) * –
MULS.W Rm,Rn
0010nnnnmmmm1111 Signed operation of Rn × Rm –
→ MACL
16 × 16 → 32 bits
1( to 3)* –
MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of
–
Rn × Rm → MACL
16 × 16 → 32 bits
1(to 3)* –
NEG
Rm,Rn
0110nnnnmmmm1011 0–Rm→Rn
–
1
–
NEGC Rm,Rn 0110nnnnmmmm1010 0–Rm–T→Rn, Borrow→T
–
1
Borrow
SUB
Rm,Rn
0011nnnnmmmm1000 Rn–Rm→Rn
–
1
–
SUBC
Rm,Rn
0011nnnnmmmm1010 Rn–Rm–T→Rn, Borrow →T –
1
Borrow
SUBV
Rm,Rn
0011nnnnmmmm1011 Rn–Rm→Rn, Underflow→T –
1
Underflow
Note: * The number of execution cycles indicated within the parentheses ( ) are required when
the operation result is read from the MACH/MACL register immediately after the
instruction.
Rev. 3.00 Jan. 18, 2008 Page 70 of 1458
REJ09B0033-0300