SH7720 Datasheet, PDF (271/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Cache
5.4 Memory-Mapped Cache
To allow software management of the cache, cache contents can be read and written by means of
MOV instructions in privileged mode. The cache is mapped onto the P4 area in virtual address
space. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data
array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size
for the address array and data array, and instruction fetches cannot be performed.
5.4.1 Address Array
The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the
32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array.
In the address field, specify the entry address for selecting the entry, W for selecting the way, A
for enabling or disabling the associative operation, and H'F0 for indicating address array access.
As for W, B'00 indicates way 0, B'01 indicates way 1, B'10 indicates way 2, and B'11 indicates
way 3.
In the data field, specify the tag address, LRU bits, U bit, and V bit. Figure 5.4 shows the address
and data formats in 16-byte mode. For other cache size modes, change the entry address and Was
shown in table 5.8. The following three operations are available in the address array.
(1) Address-Array Read
Read the tag address, LRU bits, U bit, and V bit for the entry that corresponds to the entry address
and way specified by the address field of the read instruction. In reading, the associative operation
is not performed, regardless of whether the associative bit (A bit) specified in the address is 1 or 0.
(2) Address-Array Write (Non-Associative Operation)
Write the tag address, LRU bits, U bit, and V bit, specified by the data field of the write
instruction, to the entry that corresponds to the entry address and way as specified by the address
field of the write instruction. Ensure that the associative bit (A bit) in the address field is set to 0.
When writing to a cache line for which the U bit = 1 and the V bit =1, write the contents of the
cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the
data field of the write instruction. Always clear the uppermost 3 bits (bits 31 to 29) of the tag
address to 0. When 0 is written to the V bit, 0 must also be written to the U bit for that entry.
Rev. 3.00 Jan. 18, 2008 Page 209 of 1458
REJ09B0033-0300