SH7720 Datasheet, PDF (845/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
24.3.15 Hc Frame Remaining Register (USBHFR)
USBHFR is a 14-bit down counter indicating the bit time remaining in the current frame.
Initial
Bit
Bit Name Value R/W Description
31
FRT
0
R/W Frame Remaining Toggle
This bit is always loaded from the FIT bit in Hc Fm interval
when FR reaches 0. This bit is used by HCD for the
synchronization between FI and FR.
30 to 14 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
13 to 0 FR13 to FR0 All 0 R/W Frame Remaining
This counter is decremented at each bit time. When this
counter reaches 0, this counter is reset by loading the
value of the FI bit specified in USBHFI at the next bit time
boundary. When the host controller transits to the
UsbOperational state, it read the FI bit in USBHFI again
and uses the updated value from the next SOF.
Rev. 3.00 Jan. 18, 2008 Page 783 of 1458
REJ09B0033-0300