SH7720 Datasheet, PDF (1381/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 38 Electrical Characteristics
38.4.2 Control Signal Timing
Table 38.8 Control Signal Timing
Conditions: V_CCQ = 2.7 to 3.6 V, V_CCQ1 = 2.7 to 3.6 V or 1.65 to 1.95 V,
V_CC = 1.4 to 1.6 V, Ta = –20 to 75°C
Item
Symbol Min.
Max.
Unit Figure
RESETP pulse width
RESETP setup time*¹
t
RESPW
20*³

t_RESPS
23

tcyc*²*⁴ 38.8, 38.9
ns
RESETP hold time
t_RESPH
2

ns
RESETM pulse width
t
RESPW
20*³

tcyc*²*⁴
RESETM setup time*¹
t
23
RESPS

ns
RESETM hold time
t
2
RESPH

ns
BREQ setup time
t
BREQS
1/2t + 7
cyc

ns
38.10
BREQ hold time
t_BREQH
1/2t_cyc + 2 
ns
NMI setup time*¹
t
8
NMIS

ns
38.9
NMI hold time
t_NMIH
3

ns
IRQ5 to IRQ0 setup time*¹
t_IRQS
8

ns
IRQ5 to IRQ0 hold time
t_IRQH
3

ns
BACK delay time
t
BACKD
1/2t
cyc
1/2t + 13 ns
cyc
38.10, 38.11
STATUS0 delay time
t
STD

18
ns
Bus tri-state delay time 1
t
0
BOFF1
30
ns
Bus tri-state delay time 2
t
0
BOFF2
30
ns
Bus buffer-on time 1
t_BON1
0
30
ns
38.10, 38.11
Bus buffer-on time 2
t
0
BON2
30
ns
Notes: 1. RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the
clock rise when the setup time shown is used. If the setup time cannot be used,
detection may be delayed until the next clock rises.
2. The upper limits of the external bus clock are 66.67 MHz (133 MHz version).
3. In standby mode, t = t (10 ms). When the clock multiplication ratio is changed,
RESPW
SOC2
t_RESPW = t_PLL (100 µs).
4. t_cyc means the external bus clock cycle (B clock cycle).
Rev. 3.00 Jan. 18, 2008 Page 1319 of 1458
REJ09B0033-0300