SH7720 Datasheet, PDF (639/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Realtime Clock (RTC)
17.3.17 RTC Control Register 2 (RCR2)
RCR2 is a register for periodic interrupt control, 30-second adjustment ADJ, divider circuit
RESET, and RTC count control.
RCR2 is initialized to H'09 by a power-on reset. It is initialized except for RTCEN and START by
a manual reset. It is not initialized in standby mode, and retains its contents.
Bit
Bit Name Initial Value R/W Description
7
PEF
0
R/W Periodic Interrupt Flag
Indicates interrupt generation with the period
designated by the PES2 to PES0 bits. When set
to 1, PEF generates periodic interrupts.
0: Interrupts not generated with the period
designated by the bits PES2 to PES0.
[Clearing condition] When 0 is written to PEF
1: Interrupts generated with the period
designated by the PES2 to PES0 bits.
[Setting condition] When an interrupt is
generated with the period designated by the
bits PES0 to PES2 or when 1 is written to the
PEF flag
6
PES2
0
R/W Interrupt Enable Flags
5
PES1
0
R/W These bits specify the periodic interrupt.
4
PES0
0
R/W 000: No periodic interrupts generated
001: Periodic interrupt generated every 1/256
second
010: Periodic interrupt generated every 1/64
second
011: Periodic interrupt generated every 1/16
second
100: Periodic interrupt generated every 1/4
second
101: Periodic interrupt generated every 1/2
second
110: Periodic interrupt generated every 1 second
111: Periodic interrupt generated every 2
seconds
Rev. 3.00 Jan. 18, 2008 Page 577 of 1458
REJ09B0033-0300