SH7720 Datasheet, PDF (484/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
• DMARS2
Initial
Bit
Bit Name Value R/W Description
15
C5MID5 0
14
C5MID4 0
13
C5MID3 0
R/W Transfer request module ID5 to ID0 for DMA channel 5
R/W ^(MID)
R/W ^{See table 10.2.}
12
C5MID2 0
R/W
11
C5MID1 0
R/W
10
C5MID0 0
R/W
9
C5RID1 0
8
C5RID0 0
R/W Transfer request register ID1 and ID0 for DMA channel 5
R/W ^(RID)
See table 10.2.
7
C4MID5 0
6
C4MID4 0
5
C4MID3 0
R/W Transfer request module ID5 to ID0 for DMA channel 4
R/W ^(MID)
R/W ^{See table 10.2.}
4
C4MID2 0
R/W
3
C4MID1 0
R/W
2
C4MID0 0
R/W
1
C4RID1 0
0
C4RID0 0
R/W Transfer request register ID1 and ID0 for DMA channel 4
R/W ^(RID)
See table 10.2.
Rev. 3.00 Jan. 18, 2008 Page 422 of 1458
REJ09B0033-0300