SH7720 Datasheet, PDF (549/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
2
MSTP52 0
R/W Module Stop Bit 52
When the MSTP52 bit is set to 1, the supply of the clock
to the SSL is halted.
0: SSL operates
1: Clock supply to SSL halted
Note: On the models not having the SSL, this bit is
reserved. The write value should always be 1.
1
MSTP51 0
R/W Module Stop Bit 51
When the MSTP51 bit is set to 1, the supply of the clock
to the AFEIF is halted.
0: AFEIF operates
1: Clock supply to AFEIF halted
0
MSTP50 0
R/W Module Stop Bit 50
When the MSTP50 bit is set to 1, the supply of the clock
to the LCDC is halted.
0: LCDC operates
1: Clock supply to LCDC halted
Rev. 3.00 Jan. 18, 2008 Page 487 of 1458
REJ09B0033-0300