SH7720 Datasheet, PDF (1070/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 30 SIM Card Module (SIM)
3. The smart card interface then returns the data line to high impedance. The data line is held at
high level by the pull-up resistance.
4. The receive side performs a parity check.
If there is no parity error and reception is normal, reception of the next frame is awaited,
without further action.
On the other hand, when a parity error has occurred in T = 0 mode, an error signal (DE: low
level) is output, requesting data retransmission. After output of an error signal with the
specified duration, the receive side again sets the signal line to the high-impedance state. The
signal line returns to high level by means of the pull-up resistance. If in T = 1 mode, however,
no error signal is output even if a parity error occurs.
5. If the transmit side does not receive an error signal, the next frame is transmitted.
On the other hand, if in T = 0 mode and an error signal is received, the data for which the error
occurred is retransmitted as in step 2 above. In T = 1 mode, however, error signals are not
received and retransmission is not performed.
30.4.3 Register Settings
Table 30.2 shows a map of the bits in the registers used by the smart card interface.
Bits for which 0 or 1 is shown must always be set to the value shown. The method for setting the
bits other than these is explained below.
Rev. 3.00 Jan. 18, 2008 Page 1008 of 1458
REJ09B0033-0300