SH7720 Datasheet, PDF (146/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
Table 3.2 Virtual Address Space
Address Range
Name
H'A5000000 to H'A5FFFFFF P2/Uxy
Protection
Privileged or
DSP
Description
16-Mbyte physical address space,
non-cacheable, non-address
translatable
Can be accessed in privileged mode,
privileged DSP mode, and user DSP
mode
3.2.3 CPU Register Sets
In DSP mode, the status register (SR) in the CPU unit is extended to add control bits and three
control registers: a repeat start register (SR), repeat end register (RE), and modulo register (MOD)
are added as control registers.
31 30 29 28 27
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0 MD RB BL
RC[11:0]
0 0 0 DSP DMY DMX M Q I3 I2 I1 I0 RF1 RF0 S
31
RS
0
Repeat start register (RS)
0
Status Register
T _(SR)
31
RE
0
Repeat end register (RE)
31
16 15
ME
MS
0
MODulo register (MOD)
Figure 3.2 CPU Registers in DSP Mode
Rev. 3.00 Jan. 18, 2008 Page 84 of 1458
REJ09B0033-0300