SH7720 Datasheet, PDF (534/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Watchdog Timer (WDT)
Initial
Bit
Bit Name Value R/W Description
7
TME
0
R/W Timer Enable
Starts and stops timer operation. Clear this bit to 0 when
using the WDT in software standby mode or when
changing the clock frequency.
0: Timer disabled: Count-up stops and WTCNT value is
retained
1: Timer enabled
6
WT/IT
0
R/W Timer Mode Select
Selects whether to use the WDT as a watchdog timer or
an interval timer.
0: Interval timer mode
1: Watchdog timer mode
Note: If WT/IT is modified when the WDT is operating,
the up-count may not be performed correctly.
5
RSTS
0
R/W Reset Select
Selects the type of reset when the WTCNT overflows in
watchdog timer mode. In interval timer mode, this setting
is ignored.
0: Power-on reset
1: Manual reset
4
WOVF 0
R/W Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in watchdog
timer mode. This bit is not set in interval timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
3
IOVF
0
R/W Interval Timer Overflow
Indicates that the WTCNT has overflowed in interval timer
mode. This bit is not set in watchdog timer mode.
0: No overflow
1: WTCNT has overflowed in interval timer mode
Rev. 3.00 Jan. 18, 2008 Page 472 of 1458
REJ09B0033-0300