SH7720 Datasheet, PDF (1050/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 30 SIM Card Module (SIM)
Figure 30.1 shows a block diagram of the smart card interface.
Module data bus
Peripheral bus
SIM_D
SIM_CLK
SIM_RST
SCRDR
SCTDR
SCRSR
Parity check
SCTSR
Parity
generation
SCSMR
SCSCR
SCSSR
SCSCMR
SCSC2R
SCWAIT
SCGRD
SCBRR
SCSMPL
Baud rate
generator
Serial clock
ERI
TXI
RXI
TEI
Receive data full
Transmit data empty
[Legend]
SCSCMR: Smart card mode register
SCRSR: Receive shift register
SCRDR: Receive data register
SCTSR: Transmit shift register
SCTDR: Transmit data register
SCSMR: Serial mode register
SCSCR: Serial control register
SCSC2R: Serial control 2 register
SCSSR: Serial status register
SCBRR: Bit rate register
SCWAIT: Wait time register
SCGRD: Guard extension register
SCSMPL: Sampling register
Pφ
Interrupt
controller
DMA controller
Figure 30.1 Smart Card Interface
Rev. 3.00 Jan. 18, 2008 Page 988 of 1458
REJ09B0033-0300