SH7720 Datasheet, PDF (438/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less
than the RTCOR value will enable refreshing to be started immediately.
After self-refreshing has been set, the self-refresh state continues even if the chip standby state is
entered using the LSI standby function, and is maintained even after recovery from standby mode
by an interrupt.
The self-refresh state is not cleared by a manual reset.
In case of a power-on reset, the bus state controller's registers are initialized, and therefore the
self-refresh state is cleared.
CKIO
CKE
A25 to A0
A12/A11*¹
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Tp
Tpw
Trr
Trc
Hi-z
Trc
Trc
Trc
Trc
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.26 Self-Refresh Timing
Rev. 3.00 Jan. 18, 2008 Page 376 of 1458
REJ09B0033-0300