SH7720 Datasheet, PDF (37/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 9.5 Continuous Access for Normal Space 2, Bus Width = 16 bits, Longword Access,
CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0) ...................................... 340
Figure 9.6 Example of 32-Bit Data-Width SRAM Connection .................................................. 341
Figure 9.7 Example of 16-Bit Data-Width SRAM Connection .................................................. 342
Figure 9.8 Example of 8-Bit Data-Width SRAM Connection.................................................... 342
Figure 9.9 Wait Timing for Normal Space Access (Software Wait Only) ................................. 343
Figure 9.10 Wait State Timing for Normal Space Access
(Wait State Insertion using WAIT Signal) .............................................................. 344
Figure 9.11 CSn Assert Period Expansion.................................................................................. 345
Figure 9.12 Example of 32-Bit Data-Width SDRAM Connection ............................................. 347
Figure 9.13 Example of 16-Bit Data-Width SDRAM Connection ............................................. 348
Figure 9.14 Burst Read Basic Timing (Auto-Precharge)............................................................ 361
Figure 9.15 Burst Read Wait Specification Timing (Auto-Precharge)....................................... 362
Figure 9.16 Basic Timing for Single Read (Auto-Precharge)..................................................... 363
Figure 9.17 Basic Timing for Burst Write (Auto-Precharge) ..................................................... 365
Figure 9.18 Basic Timing for Single Write (Auto-Precharge).................................................... 366
Figure 9.19 Burst Read Timing (No Auto-Precharge)................................................................ 368
Figure 9.20 Burst Read Timing (Bank Active, Same Row Address) ......................................... 369
Figure 9.21 Burst Read Timing (Bank Active, Different Row Addresses) ................................ 370
Figure 9.22 Single Write Timing (No Auto-Precharge) ............................................................. 371
Figure 9.23 Single Write Timing (Bank Active, Same Row Address) ....................................... 372
Figure 9.24 Single Write Timing (Bank Active, Different Row Addresses) .............................. 373
Figure 9.25 Auto-Refresh Timing .............................................................................................. 375
Figure 9.26 Self-Refresh Timing ................................................................................................ 376
Figure 9.27 Access Timing in Power-Down Mode .................................................................... 378
Figure 9.28 Write Timing for SDRAM Mode Register (Based on JEDEC)............................... 381
Figure 9.29 EMRS Command Issue Timing............................................................................... 384
Figure 9.30 Transition Timing in Deep Power-Down Mode...................................................... 385
Figure 9.31 Burst ROM (Clock Asynchronous) Access
(Bus Width = 32 Bits, 16-byte Transfer (Number of Bursts = 4),
Access Wait for First Time = 2, Access Wait for 2nd Time and after = 1) ............. 387
Figure 9.32 Basic Access Timing for Byte-Selection SRAM (BAS = 0) ................................... 388
Figure 9.33 Basic Access Timing for Byte-Selection SRAM (BAS = 1) ................................... 389
Figure 9.34 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)............. 390
Figure 9.35 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM ............... 391
Figure 9.36 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............... 391
Figure 9.37 Example of PCMCIA Interface Connection............................................................ 393
Figure 9.38 Basic Access Timing for PCMCIA Memory Card Interface................................... 394
Rev. 3.00 Jan. 18, 2008 Page xxxvii of lxii