SH7720 Datasheet, PDF (683/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
(5) Transmitting and Receiving Data (Serial data reception)
Figures 18.7 and 18.8 show sample serial reception flowcharts. After SCIF reception is enabled,
use the following procedure to perform serial data reception.
Start reception
Read PER and FER
flags in SCSSR
PER or FER = 1?
(1)
Yes
(1) Receive error handling and break
detection:
Read the DR, ER, and BRK flags in
SCSSR2 to identify any error, perform
the appropriate error handling, then
clear the DR, ER, and BRK flags to 0.
In the case of a framing error, a break
can also be detected by reading the
value of the RxD2 pin.
No
Error processing
(2) SCIF status check and receive data
Read RDF flag in SCSSR
(2)
read :
Read the serial status register
(SCSSR) and check that RDF = 1, then
No
RDF = 1?
read the receive data in the receive
FIFO data register (SCFRDR), read 1
from the RDF flag, and then clear the
Yes
RDF flag to 0.
Read receive data in SCFRDR,
and clear RDF flag in
(3)
SCSSR to 0
(3) Serial reception continuation
procedure:
To continue serial reception, read at
least the receive trigger set number of
receive data bytes from SCFRDR, read
1 from the RDF flag, then clear the
No
All data received?
RDF flag to 0. The number of receive
data bytes in SCFRDR can be
ascertained by reading the lower bits of
Yes
SCFDR.
Clear RE bit in SCSCR to 0
End reception
Figure 18.7 Sample Serial Reception Flowchart (1)
Rev. 3.00 Jan. 18, 2008 Page 621 of 1458
REJ09B0033-0300