SH7720 Datasheet, PDF (1093/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
31.3.1 Mode Register (MODER)
MODER specifies the MMCIF operating mode. The MMCIF has an operating mode: MMC mode.
Three signals, clock, command, and data signals, are used as the interfaces between the host
system and the MMC in MMC mode. The clock signal is used to make the host system and the
MMC synchronize each other. The command signal is used to issue a command from the host
system to the MMC and send a response from the MMC to the host system. The data signal is
used to write data to and read data from the MMC. The command and data signals are
bidirectional buses.
The following sequence should be repeated when the MMCIF uses the MMC: Send a command,
wait for the end of the command sequence and the end of the data busy state, and send the next
command.
Bit
7 to 1
0
Initial
Bit Name Value

All 0

0
R/W Description
 Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Reserved
The write value should always be 0.
31.3.2 Command Type Register (CMDTYR)
CMDTYR specifies the command format in conjunction with RSPTYR. Bits TY1 and TY0
specify the existence and direction of transfer data, and bits TY6 to TY2 specify the additional
settings. All of bits TY6 to TY2 should be cleared to 0 or only one of them should be set to 1. Bits
TY6 to TY2 can only be set to 1 if the corresponding settings in bits TY1 and TY0 allow that
setting. If this register is not set correctly, operation cannot be guaranteed.
To perform single-block transfer, bits TY1 and TY0 should be set to 01 or 10 and bits TY6 to TY2
to 0.
Rev. 3.00 Jan. 18, 2008 Page 1031 of 1458
REJ09B0033-0300