SH7720 Datasheet, PDF (514/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(overrun 0,
high level)
DACK
(high active)
CPU
First acceptance
CKIO
DMAC write or read
Dead zone
Second acceptance Third acceptance
Dead zone
Dead zone
Acceptance
started
Acceptance
started
Bus cycle
CPU
DMAC write or read
DREQ
(overrun 1,
high level)
DACK
(active-high)
First acceptance Second acceptance
Dead zone
Dead zone
Acceptance started
Third acceptance
Dead zone
Acceptance started
Figure 10.22 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles and So DREQ
Sampling is Accepted Normally)
10.5.3 Other Notes
1. Before making a transition to standby mode, either wait until DMA transfer finishes or
suspend DMA transfer.
2. If an on-chip peripheral module whose clock supply is to be stopped by the module standby
function is performing DMA transfer, either wait until DMA transfer finishes or suspend DMA
transfer before making a transition to module standby mode.
3. Do not write to SAR, DAR, DMATCR, or DMARS during DMA transfer.
Concerning Above Notes 1 and 2:
DMA transfer end can be confirmed by checking whether the TE bit in CHCR is set to 1.
To suspend DMA transfer, clear the DE bit in CHCR to 0.
Rev. 3.00 Jan. 18, 2008 Page 452 of 1458
REJ09B0033-0300