SH7720 Datasheet, PDF (881/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 USB Function Controller (USBF)
25.3.12 Interrupt Enable Register 1 (IER1)
IER1 enables the interrupt requests of the interrupt flag register 1. When an interrupt flag is set to
1 while the corresponding bit of each interrupt is set to 1, the interrupt request set in the interrupt
select register 1 is issued.
Bit Bit Name
7 to 3 
2
EP3 TR IE
1
EP3 TS IE
0
VBUSF IE
Initial Value R/W Description
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W EP3 TR Interrupt Enable
0
R/W EP3 TS Interrupt Enable
0
R/W VBUSF Interrupt Enable
25.3.13 Interrupt Enable Register 2 (IER2)
IER2 enables the interrupt requests of the interrupt flag register 2. When an interrupt flag is set to
1 while the corresponding bit of each interrupt is set to 1, the interrupt request set in the interrupt
select register 2 is issued.
Bit Bit Name
7 to 5 
4
SURSE IE
3
CFDN IE
2
SOFE IE
1
SETCE IE
0
SETIE IE
Initial Value R/W Description
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
0
R/W SURSE Interrupt Enable
0
R/W CFDN Interrupt Enable
0
R/W SOFE Interrupt Enable
0
R/W SETCE Interrupt Enable
0
R/W SETIE Interrupt Enable
Rev. 3.00 Jan. 18, 2008 Page 819 of 1458
REJ09B0033-0300