SH7720 Datasheet, PDF (1141/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
Input/output pins
CLK
CMD
DAT
CMDSTRT
(START)
OPCR
(DA TA EN)
(CMDOFF)
INTSTR0
(CMDI)
(CRPI)
(DTI)
(DRPI)
(DBSYI)
(FEI)
CSTR
(CWRE)
(BUSY)
(FIFO_EMPTY)
(DTBUSY)
(DTBUSY_TU)
CMD24 (WRITE_SINGLE_BLOCK)
Transfer clock
transmission halted
Transfer clock
transmission resumed
Command
transmission
started
Write data
Block data
transmission
suspended
Write data
Block data
transmission
resumed
Writing data to FIFO
Busy
Single block write command execution sequence
(REQ)
Figure 31.16 Example of Command Sequence for Commands with Write Data
(Block Size > FIFO Size)
Rev. 3.00 Jan. 18, 2008 Page 1079 of 1458
REJ09B0033-0300