SH7720 Datasheet, PDF (273/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Cache
(2) Data-Array Write
Write the longword data specified by the data filed, to the position specified by L of the address
field, in the entry that corresponds to the entry address and the way specified by the address field.
(1) Address array access
(a) Address specification
Read access
31
24
1111 0000
23
14
*--------*
13 12
W
11
4
Entry address
Write access
31
24
1111 0000
23
14
*--------*
13 12
W
11
4
Entry address
3
2
0
0
*00
3
2
0
A
*00
(b) Data specification (both read and write accesses)
31
Tag address (31 to 10)
10 9
4
LRU
3
2
XX
1
0
UV
(2) Data array access (both read and write accesses)
(a) Address specification
31
24
23
14 13 12
1111 0001
*--------*
W
11
4
Entry address
(b) Data specification
31
Longword
3
21
0
L
00
0
*: Don’t care bit
X: 0 for read, don’t care for write
Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access
(16-kbyte mode)
Table 5.8 Address Format Based on the Size of Cache to be Assigned to Memory
Cache Size
16 kbytes
32 kbytes
Entry Address Bits
11 to 4
12 to 4
W Bit
13 and 12
14 to 13
Rev. 3.00 Jan. 18, 2008 Page 211 of 1458
REJ09B0033-0300