SH7720 Datasheet, PDF (20/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

17.3.11 Hour Alarm Register (RHRAR) ........................................................................... 571
17.3.12 Day of Week Alarm Register (RWKAR) ............................................................. 572
17.3.13 Date Alarm Register (RDAYAR)......................................................................... 573
17.3.14 Month Alarm Register (RMONAR) ..................................................................... 574
17.3.15 Year Alarm Register (RYRAR)............................................................................ 574
17.3.16 RTC Control Register 1 (RCR1)........................................................................... 575
17.3.17 RTC Control Register 2 (RCR2)........................................................................... 577
17.3.18 RTC Control Register 3 (RCR3)........................................................................... 579
17.4 Operation ........................................................................................................................... 580
17.4.1 Initial Settings of Registers after Power-On ......................................................... 580
17.4.2 Setting Time ......................................................................................................... 580
17.4.3 Reading Time........................................................................................................ 581
17.4.4 Alarm Function..................................................................................................... 582
17.5 Usage Notes ....................................................................................................................... 583
17.5.1 Register Writing during RTC Count..................................................................... 583
17.5.2 Use of Realtime Clock (RTC) Periodic Interrupts................................................ 583
17.5.3 Transition to Standby Mode after Setting Register............................................... 583
17.5.4 Crystal Oscillator Circuit ...................................................................................... 584
Section 18 Serial Communication Interface with FIFO (SCIF).......................... 585
18.1 Features.............................................................................................................................. 585
18.2 Input/Output Pins............................................................................................................... 588
18.3 Register Descriptions......................................................................................................... 589
18.3.1 Receive Shift Register (SCRSR) .......................................................................... 590
18.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 590
18.3.3 Transmit Shift Register (SCTSR) ......................................................................... 590
18.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 590
18.3.5 Serial Mode Register (SCSMR)............................................................................ 591
18.3.6 Serial Control Register (SCSCR).......................................................................... 595
18.3.7 FIFO Error Count Register (SCFER) ................................................................... 599
18.3.8 Serial Status Register (SCSSR) ............................................................................ 600
18.3.9 Bit Rate Register (SCBRR) .................................................................................. 607
18.3.10 FIFO Control Register (SCFCR) .......................................................................... 609
18.3.11 FIFO Data Count Register (SCFDR).................................................................... 612
18.3.12 Transmit Data Stop Register (SCTDSR) .............................................................. 613
18.4 Operation ........................................................................................................................... 613
18.4.1 Asynchronous Mode ............................................................................................. 613
18.4.2 Serial Operation .................................................................................................... 614
18.4.3 Synchronous Mode ............................................................................................... 624
18.4.4 Serial Operation in Synchronous Mode ................................................................ 625
Rev. 3.00 Jan. 18, 2008 Page xx of lxii