SH7720 Datasheet, PDF (207/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

39 31
0
Guard
Source 1 or 2
H'00008000
Section 3 DSP Operating Unit
ALU
GT Z N V DC
DSR
Guard
39 31
Cleared to 0
0
Figure 3.20 Rounding Operation Flow
Rounded result
H'00 0002
H'00 0001
0
Analog value
True value
Figure 3.21 Definition of Rounding Operation
Table 3.30 Variation of Rounding Operation
Mnemonic
PRND
Function
Rounding
Source 1
Sx

Source 2

Sy
Destination
Dz
Dz
• Overflow Protection
The S bit in SR is effective for any rounding operations in the DSP unit. See section 3.5.11,
Overflow Protection, for details.
Rev. 3.00 Jan. 18, 2008 Page 145 of 1458
REJ09B0033-0300