SH7720 Datasheet, PDF (862/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
24.5.2 Restriction on the Memory Access Address
MPS in ED, CBP in General TD, and BP0 and OFFSET0 to 7 in Ischoronous TD must be set in
multiples of 4 (4n). In the OpenHCI standard, 1 packet is transferred by ITD in General TD and 1
packet by 1 offset in Ischronous TD during IN transfer. In addition, when the amount of the data
specified by TD during OUT transfer exceeds MAXPACKETSIZE (MPS), a packet transmission
is carried out in MAXPACKETSIZE. Therefore, the setting value can be made as above. This
restriction is due to the difference between the specifications of the HCI interface which is the
standard of the IP bus interface of USB and of the bus interface of this LSI. Data might be
correctly written to if data is transferred from addresses other than 4n address. For example, when
a two-byte transfer is carried out from the address that terminates at 1, a long-word transfer is
carried out and an unexpected data is written to starting address 0.
24.6 Accessing External Address from the USB Host
Accessing the external address from the USB Host is carried out as follows:
• When reading, 4, 8, 12, or 16-byte transfer in longword units.
• When writing, 1 to 16-byte transfer.
Rev. 3.00 Jan. 18, 2008 Page 800 of 1458
REJ09B0033-0300