SH7720 Datasheet, PDF (836/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
24.3.4 Hc Interrupt Status Register (USBHIS)
This register indicates the status in various events that cause hardware interrupts. When an event
occurs, the host controller sets the corresponding bit in this register. When the bit is set to 1, a
hardware interrupt is generated while an interrupt is enabled and the MIE bit is set in USBHIE
(section 24.3.5, Hc Interrupt Enable Register (USBHIE)). HCD clears a specified bit in this
register by writing 1 in the bit position to be cleared. The host controller driver cannot set any bit
of these bits. The host controller never clears bits.
Bit
Bit Name
31

30
OC
29 to 7 
6
RHSC
5
FNO
Initial
Value R/W Description
0
R Reserved
This bit is always read as 0. The write value should always
be 0.
0
R/W Ownership Change
This bit is set by the host controller when the OCR bit in
USBHCS is set. This event generates a system
management interrupt (SMI) at once when not masked.
When there is no SMI pin, this bit is set to 0.
0: The OCR bit in USBHCS is not set
1: The OCR bit in USBHCS is set
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0
R/W Root Hub Status Change
This bit is set when the content of USBHRS or the content
of any USBHRPS 1, 2 register has changed.
0: The content of USBHRS or USBHRPS is not changed
1: The content of USBHRS or USBHRPS is changed
0
R/W Frame Number Overflow
This bit is set when MSB (bit 15) in USBHFN changes
value from 0 to 1 or from 1 to 0 or the Hcca Frame
Number bit is updated.
0: MSB or the Hcca Frame Number bit in USBHFN is not
updated
1: MSB or the Hcca Frame Number bit in USBHFN is
updated
Rev. 3.00 Jan. 18, 2008 Page 774 of 1458
REJ09B0033-0300