SH7720 Datasheet, PDF (888/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 USB Function Controller (USBF)
Bit Bit Name Initial Value R/W Description
3, 2 

W Reserved
The write value should always be 0.
1
EP0o CLR 
W EP0o Clear
0
EP0i CLR 
W EP0i Clear
25.3.30 FIFO Clear Register 1 (FCLR1)
FCLR is a one shot register to clear the FIFO buffers for endpoints 4 and 5. Writing 1 to a bit
clears the data in the corresponding FIFO buffer.
The corresponding interrupt flag is not cleared by this clear instruction. Do not clear a FIFO buffer
during transmission and reception.
Bit Bit Name
7 to 5 
4
EP5 CCLR
3, 2 
1
EP5 CLR
0
EP4 CLR
Initial Value R/W Description

W Reserved
The write value should always be 0.

W EP5 CPU Clear

W Reserved
The write value should always be 0.

W EP5 Clear

W EP4 Clear
25.3.31 DMA Transfer Setting Register (DMA)
DMA is set when the dual address transfer is used to the data register for endpoints 1 and 2 to
which transfer is possible by DMA. The USB1_pwr_en pin level can be controlled by the bit 2.
Bit Bit Name
7 to 3 
2
PULLUP E
Initial Value R/W Description
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W Pull-up Enable
Controls connection notification to USB host/hub.
0: USB1_pwr_en pin goes high
1: USB1_pwr_en pin goes low
Rev. 3.00 Jan. 18, 2008 Page 826 of 1458
REJ09B0033-0300