SH7720 Datasheet, PDF (355/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Initial
Bit Bit Name Value R/W Description
4

1
R Reserved
This bit is always read as 1. The write value should always
be 1.
3
ENDIAN 0/1* R Endian Flag
Samples the external pin for specifying endian on power-on
reset (MD5). All address spaces are defined by this bit. This
is a read-only bit.
0: The external pin for specifying endian (MD5) was low level
on power-on reset. This LSI is being operated as big
endian.
1: The external pin for specifying endian (MD5) was high
level on power-on reset. This LSI is being operated as
little endian.
2

0
R Reserved
This bit is always read as 0. The write value should always
be 0.
1
HIZMEM 0
R/W High-Z Memory Control
Specifies the pin state in standby mode for A25 to A0, BS,
CSn, RD/WR, WEn(BEn)/DQMxx, and RD. When a bus is
released, these pins enter the high-impedance state
regardless of the setting of this bit.
0: High impedance in standby mode
1: Driven in standby mode
0
HIZCNT 0
R/W High-Z Control
Specifies the state in standby mode and bus released for
CKIO, CKE, RAS, and CAS.
0: High impedance in standby mode and bus released for
CKIO, CKE, RAS, and CAS.
1: Driven in standby mode and bus released for CKIO, CKE,
RAS, and CAS.
Note: * The external pin (MD5) for specifying endian is sampled on power-on reset. When big
endian is specified, this bit is read as 0 and when little endian is specified, this bit is
read as 1.
Rev. 3.00 Jan. 18, 2008 Page 293 of 1458
REJ09B0033-0300