SH7720 Datasheet, PDF (353/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
9.4.1 Common Control Register (CMNCR)
CMNCR is a 32-bit register that controls the common items for each area. Do not access external
memory other than area 0 until the CMNCR initialization is complete.
Initial
Bit
Bit Name Value
31 to 15 
All 0
14
BSD
0
13

0
12
MAP
0
11
BLOCK 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Bus Access Start Timing Specification After Bus
Acknowledge
Specifies the bus access start timing after the external bus
acknowledge signal is received.
0: Starts the external access at the same timing as the
address drive start after the bus acknowledge signal is
received.
1: Starts the external access one cycle following the address
drive start after the bus acknowledge signal is received.
R Reserved
This bit is always read as 0. The write value should always be
0.
R/W Space Specification
Selects the address map for the external address space. The
address maps to be selected are shown in tables 9.2 and 9.3.
0: Selects address map 1
1: Selects address map 2
R/W Bus Lock Bit
Specifies whether or not the BREQ signal is received.
0: Receives BREQ
1: Does not receive BREQ
Rev. 3.00 Jan. 18, 2008 Page 291 of 1458
REJ09B0033-0300