SH7720 Datasheet, PDF (302/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 7 Exception Handling
Table 7.5 Instruction Where a Specific Exception Occurs When a Memory Access
Exception Occurs in Repeat Control (SR.RC[11:0]≥1)
Instruction Where an
Exception Occurs
1
Number of Instructions in a Repeat Loop
2
3
4 or Greater
RptDtct




RptDtct1
Instruction/data Instruction/data Instruction/data Instruction/data
access
access
access
access
RptDtct2

Instruction/data Instruction/data Instruction/data
access
access
access
RptDtct3


Instruction/data Instruction/data
access
access
Note:
The following labels are used here.
RptDtct: Repeat detection instruction address
RptDtct1: Instruction address immediately after the repeat detect instruction
RptDtct2: Second instruction address from the repeat detect instruction
RptDtct3: Third instruction address from the repeat detect instruction
(5) MMU Exception in Repeat Control Period
If an MMU exception occurs in the repeat control period, a specific exception code is generated as
well as a CPU address error. For a TLB miss exception, TLB invalid exception, and initial page
write exception, an exception code (H'070) indicating the repeat loop period is specified in the
EXPEVT. For a TLB protection exception, an exception code (H'0D0) is specified in the
EXPEVT. In a TLB miss exception, vector offset is specified as H'00000100.
An instruction where an exception occurs and the SPC value to be saved are the same as those for
the CPU address error.
After this exception processing, the repeat control cannot be returned correctly. To execute a
repeat loop correctly, care must be taken not to generate an MMU related exception in the repeat
control period.
Note:
In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction. The restriction occurs when SR.RC[11:0] ≥ 1.
Rev. 3.00 Jan. 18, 2008 Page 240 of 1458
REJ09B0033-0300