SH7720 Datasheet, PDF (1009/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 27 A/D Converter
Condition: The problem arises in the following cases. Also see the table below:
(a) In Single/Multi Mode
The problem arises when A/D conversion is started while the setting of the
ADCSR.DMASL bit is 1, after having proceeded while the setting of the DMASL bit
was 0 and then stopped.
(b) In Scan Mode
The problem arises when A/D conversion is started while the setting of the
ADCSR.DMASL bit is 1, after having proceeded and stopped.
Table 27.4 Conditions for the Method of Transferring Results of A/D Conversion and
Inclusion of Superfluous DMA
The Next Conversion
Current Conversion
Single Mode/ DMASL = 0
Multi Mode DMASL = 1
Scan Mode DMASL = 0
DMASL = 1
In Single/Multi Mode
DMASL = 0 DMASL = 1
Normal
Normal
Normal
Normal
Faulty
Normal
Faulty
Faulty
In Scan Mode
DMASL = 0 DMASL = 1
Normal
Normal
Normal
Normal
Faulty
Normal
Faulty
Faulty
Avoiding the Problem: Follow either of procedures (a) or (b) below.
(a) After A/D conversion has stopped, initialize the ADC by placing it in the module standby
state. Start the next round of A/D conversion after releasing the ADC from the module
standby state.
(b) Operation under the following conditions ensures that the problem will not arise.
• In Single/Multi Mode
Transfer when DMASL = 0 → Transfer when DMASL = 0
Transfer when DMASL = 1 → Transfer when DMASL = 1
• In Scan Mode
Transfer when DMASL = 0 → Transfer when DMASL = 0
Rev. 3.00 Jan. 18, 2008 Page 947 of 1458
REJ09B0033-0300