SH7720 Datasheet, PDF (513/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(overrun 0,
high level)
DACK
(active-high)
CPU
First acceptance
Dead zone
CKIO
DMAC write or read
Second
acceptance
Third acceptance (possible)
Dead zone
Acceptance started
Bus cycle
DREQ
(overrun 1,
high level)
DACK
(active-high)
CPU
Second
First acceptance _acceptance
DMAC write or read
Third acceptance (possible)
Dead zone Dead zone
Acceptance
started
Figure 10.21 Timing of DREQ Input Detection by Level Detection in Cycle Stealing Mode
(DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles and So
DREQ Sampling is Accepted One Extra Time)
Rev. 3.00 Jan. 18, 2008 Page 451 of 1458
REJ09B0033-0300