SH7720 Datasheet, PDF (906/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 USB Function Controller (USBF)
• Status Stage (Control-Out)
USB function
IN token reception
Application
Valid data
in EP0i FIFO?
Yes
No
NAK
Interrupt request
0-byte transmission to host
ACK
Clear EP0i transfer
request flag
(IFR0/EP0i TR = 0)
Write 1 to EP0i packet
enable bit
(TRG/EP0i PKTE = 1)
Set EP0i transmission
complete flag
(IFR0/EP0i TS = 1)
Interrupt request
Clear EP0i transmission
complete flag
(IFR0/EP0i TS = 0)
End of control transfer
End of control transfer
Figure 25.10 Status Stage (Control-Out) Operation
The control-out status stage starts with an IN token from the host. When an IN-token is received at
the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer
request interrupt is generated. The application recognizes from this interrupt that the status stage
has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable
bit but no data is written to the EP0i FIFO. As a result, the next IN token causes 0-byte data to be
transmitted to the host, and control transfer ends.
After the application has finished all processing relating to the data stage, 1 should be written to
the EP0i packet enable bit.
Rev. 3.00 Jan. 18, 2008 Page 844 of 1458
REJ09B0033-0300