SH7720 Datasheet, PDF (610/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Compare Match Timer (CMT)
Figure 16.1 shows a block diagram of the CMT.
CMSTR
Pφ
Pre-scaller
CMT
CH0
CMCNT_0
CMCOR_0
CMCSR_0
Pre-scaller
CMCNT_1
Interrupt control
CH1
CMCOR_1
Internal interrupt
DMA transfer
CMCSR_1
Pre-scaller
CMCNT_2
Interrupt control
CH2
CMCOR_2
Internal interrupt
DMA transfer
CMCSR_2
Pre-scaller
CMCNT_3
Interrupt control
CH3
CMCOR_3
Internal interrupt
DMA transfer
CMCSR_3
Pre-scaller
CMCNT_4
Interrupt control
CH4
CMCOR_4
Internal interrupt
DMA transfer
CMCSR_4
Interrupt control
Internal interrupt
DMA transfer
[Legend]
CMSTR: Compare match timer start register
CMCSR: Compare match timer control/status register
CMCNT: Compare match timer counter
CMCOR: Compare match timer constant register
Figure 16.1 Block Diagram of CMT
Rev. 3.00 Jan. 18, 2008 Page 548 of 1458
REJ09B0033-0300