SH7720 Datasheet, PDF (113/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 2.6 shows the control register configuration.
Section 2 CPU
Save status register (SSR)
31
0
SSR
Save program counter (SPC)
31
0
SPC
Global base register (GBR)
31
0
GBR
Vector base register (VBR)
31
0
VBR
Status register (SR)
31
0 MD RB BL 0
0
0 M Q I3 I2 I1 I0 0 0 S T
Figure 2.6 Control Register Configuration
2.4 Data Formats
2.4.1 Register Data Format
Register operands are always longwords (32 bits). When the memory operand is only a byte (8
bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31
0
Longword
Rev. 3.00 Jan. 18, 2008 Page 51 of 1458
REJ09B0033-0300