SH7720 Datasheet, PDF (578/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 15 16-Bit Timer Pulse Unit (TPU)
• Timer counter_2 (TCNT_2)
• Timer general register A_2 (TGRA_2)
• Timer general register B_2 (TGRB_2)
• Timer general register C_2 (TGRC_2)
• Timer general register D_2 (TGRD_2)
Channel 3:
• Timer control register_3 (TCR_3)
• Timer mode register_3 (TMDR_3)
• Timer I/O control register_3 (TIOR_3)
• Timer interrupt enable register_3 (TIER_3)
• Timer status register_3 (TSR_3)
• Timer counter_3 (TCNT_3)
• Timer general register A_3 (TGRA_3)
• Timer general register B_3 (TGRB_3)
• Timer general register C_3 (TGRC_3)
• Timer general register D_3 (TGRD_3)
• Timer start register (TSTR)
15.3.1 Timer Control Registers (TCR)
The TCR registers are 16-bit registers that control the TCNT channels. The TPU has four TCR
registers, one for each of channels 0 to 3. The TCR registers are initialized to H'0000 by a reset,
but not initialized in standby mode, sleep mode, or module standby.
TCR register settings should be made only when TCNT operation is stopped.
Rev. 3.00 Jan. 18, 2008 Page 516 of 1458
REJ09B0033-0300