SH7720 Datasheet, PDF (1156/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
[1]
[2]
Yes
Is CRCERI interrupt
generated?
No
Yes
Is DTERI interrupt
generated?
No
No
Is DTI interrupt
generated?
Yes
No
*
TBNCR = n(DTI)?
Yes
Write 1 to RD_CONTI
No
Is BTI interrupt
generated?
Yes
Set DMACR to H'84
No _{Does DMA transfer}
end?
Yes
Write 1 to CMDOFF
Set DMACR to H'00
Write 1 to CMDOFF
Execute CMD12
Set DMACR to H'00
FIFO clear
Write 1 to CMDOFF
Set DMACR to H'00
Command sequence end
Note: * n(DTI): The number of DTIs from the start of read sequence
Figure 31.25 Operational Flowchart for Read Sequence
(Pre-defined Multiblock Transfer) (2)
Rev. 3.00 Jan. 18, 2008 Page 1094 of 1458
REJ09B0033-0300