SH7720 Datasheet, PDF (611/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Compare Match Timer (CMT)
16.2 Register Descriptions
The CMT has the following registers. Refer to section 37, List of Registers, for more details on the
addresses and states of these registers in each operating mode. Notation for the CMT registers
takes the form XXX_N, where XXX including the register name and N indicating the channel
number. For example, CMCSR_0 denotes the CMCSR for channel 0.
(1) Common
• Compare match timer start register (CMSTR)
(2) Channel 0
• Compare match timer control/status register_0 (CMCSR_0)
• Compare match timer counter_0 (CMCNT_0)
• Compare match timer constant register_0 (CMCOR_0)
(3) Channel 1
• Compare match timer control/status register_1 (CMCSR_1)
• Compare match timer counter_1 (CMCNT_1)
• Compare match timer constant register_1 (CMCOR_1)
(4) Channel 2
• Compare match timer control/status register_2 (CMCSR_2)
• Compare match timer counter_2 (CMCNT_2)
• Compare match timer constant register_2 (CMCOR_2)
(5) Channel 3
• Compare match timer control/status register_3 (CMCSR_3)
• Compare match timer counter_3 (CMCNT_3)
• Compare match timer constant register_3 (CMCOR_3)
(6) Channel 4
• Compare match timer control/status register_4 (CMCSR_4)
• Compare match timer counter_4 (CMCNT_4)
• Compare match timer constant register_4 (CMCOR_4)
Rev. 3.00 Jan. 18, 2008 Page 549 of 1458
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