SH7720 Datasheet, PDF (1250/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 35 I/O Ports
35.5.2 Port E Data Register (PEDR)
PEDR is a register that stores data for pins PTE6 to PTE0. Bits PE6DT to PE0DT correspond to
pins PTE6 to PTE0. When the pin function is general output port, if the port is read, the value of
the corresponding PEDR bit is returned directly. When the function is general input port, if the
port is read the corresponding pin level is read.
Initial
Bit Bit Name Value R/W Description
7

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
6
PE6DT 0
R/W Table 35.5 shows the function of PEDR.
5
PE5DT 0
R/W
4
PE4DT 0
R/W
3
PE3DT 0
R/W
2
PE2DT 0
R/W
1
PE1DT 0
R/W
0
PE0DT 0
R/W
Table 35.5 Port E Data Register (PEDR) Read/Write Operations
PECR State
PEnMD1 PEnMD0 Pin State
Read
Write
0
0
Other function PEDR value Value is written to PEDR, but does not affect
pin state.
1
Output
PEDR value Write value is output from pin.
1
0
Input (Pull-up Pin state
Value is written to PEDR, but does not affect
MOS on)
pin state.
1
Input (Pull-up Pin state
Value is written to PEDR, but does not affect
MOS off)
pin state.
Note: n= 0 to 4
Rev. 3.00 Jan. 18, 2008 Page 1188 of 1458
REJ09B0033-0300