SH7720 Datasheet, PDF (38/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 9.39 Wait Timing for PCMCIA Memory Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1,
Hardware Wait = 1)................................................................................................. 395
Figure 9.40 Example of PCMCIA Space Assignment
(CS5BWCR.SA[1:0] = B'10, CS6BWCR.SA[1:0] = B'10) .................................... 396
Figure 9.41 Basic Timing for PCMCIA I/O Card Interface ....................................................... 398
Figure 9.42 Wait Timing for PCMCIA I/O Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1,
Hardware Wait = 1)................................................................................................. 399
Figure 9.43 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Waits = 3) ............................. 399
Figure 9.44 Burst ROM (Clock Synchronous) Access Timing
(Burst Length = 8, Wait Cycles inserted in First Access = 2,
Wait Cycles inserted in Second and Subsequent Accesses = 1).............................. 400
Figure 9.45 Bus Arbitration Timing ........................................................................................... 403
Section 10 Direct Memory Access Controller (DMAC)
Figure 10.1 Block Diagram of DMAC ....................................................................................... 408
Figure 10.2 DMA Transfer Flowchart........................................................................................ 425
Figure 10.3 Round-Robin Mode................................................................................................. 432
Figure 10.4 Changes in Channel Priority in Round-Robin Mode............................................... 433
Figure 10.5 Data Flow of Dual Address Mode........................................................................... 435
Figure 10.6 Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory)................................. 436
Figure 10.7 Data Flow in Single Address Mode......................................................................... 437
Figure 10.8 Example of DMA Transfer Timing in Single Address Mode ................................. 438
Figure 10.9 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection)......................................................... 439
Figure 10.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)....................................................... 440
Figure 10.11 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)....................................................... 440
Figure 10.12 Bus State when Multiple Channels are Operating................................................. 443
Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 444
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 445
Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 445
Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection .................... 446
Figure 10.17 Example of DMA Transfer End in Cycle Steal Mode Level Detection ................ 446
Figure 10.18 Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) ............................... 447
Rev. 3.00 Jan. 18, 2008 Page xxxviii of lxii