SH7720 Datasheet, PDF (533/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Watchdog Timer (WDT)
12.2 Register Descriptions for WDT
The WDT has the following two registers. Refer to section 37, List of Registers, for more details
on the addresses and states of these registers in each operating mode.
• Watchdog timer counter (WTCNT)
• Watchdog timer control/status register (WTCSR)
12.2.1 Watchdog Timer Counter (WTCNT)
WTCNT is an 8-bit readable/writable register that increments on the selected clock. When an
overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time
mode. The WTCNT counter is not initialized by an internal reset due to the WDT overflow. The
WTCNT counter is initialized to H'00 only by a power-on reset. Use a word access to write to the
WTCNT counter, with H'5A in the upper byte. Use a byte access to read WTCNT.
Note: WTCNT differs from other registers in that it is more difficult to write to. See section
12.2.3, Notes on Register Access, for details.
12.2.2 Watchdog Timer Control/Status Register (WTCSR)
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, bits to select the timer mode, and overflow flags. WTCSR holds its value in an internal
reset due to the WDT overflow. WTCSR is initialized to H'00 only by a power-on reset.
When used to count the clock settling time for canceling a software standby, it retains its value
after counter overflow. Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a
byte access to read WTCSR.
Note: WTCSR differs from other registers in that it is more difficult to write to. See section
12.2.3, Notes on Register Access, for details.
Rev. 3.00 Jan. 18, 2008 Page 471 of 1458
REJ09B0033-0300