SH7720 Datasheet, PDF (516/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 11 Clock Pulse Generator (CPG)
A block diagram of the CPG is shown in figure 11.1.
XTAL_USB
EXTAL_USB
Crystal
oscillator
CKIO
Oscillator circuit
PLL circuit 1
(×1, 2, 3, 4)
Divider 1
×1
× 1/2
× 1/3
× 1/4
× 1/6
USBH/USBF clock
Internal clock
(Iφ)
XTAL
EXTAL
MD2 to MD0
Crystal
oscillator
PLL circuit 2
(×1, 4)
CPG control unit
Clock frequency
control unit
Bus clock
(Bφ frequency is the same
as CKIO frequency.)
Peripheral clock
(Pφ)
Standby control unit
FRQCR UCLKCR
STBCR STBCR2 STBCR3 STBCR4 STBCR5
Bus interface
Internal bus
FRQCR : Frequency control register
UCKCR : USBH/USBF clock control register
STBCR : Standby control register 1
STBCR2 : Standby control register 2
STBCR3 : Standby control register 3
STBCR4 : Standby control register 4
STBCR5 : Standby control register 5
Figure 11.1 Block Diagram of CPG
Rev. 3.00 Jan. 18, 2008 Page 454 of 1458
REJ09B0033-0300