SH7720 Datasheet, PDF (511/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

• 16-byte access
• 32-bit access in an 8-bit space
• 16-bit access in an 8-bit space
• 32-bit access in a 16-bit space,
Section 10 Direct Memory Access Controller (DMAC)
Any one of the following inter-access idle cycle specifications has been made for that space:
• Idle between write cycles (IWW = 001 or more)
• Idle between read cycles in the same space (IWRRS = 001 or more)
• External wait masking (WM = 0)
Phenomena: For the access patterns above, the DREQ pin signal is detected with the timing shown
in figures 10.19 and 10.21. For other access patterns, DREQ is detected normally as shown in
figures 10.20 and 10.22.
(3) How to Avoid the Problem
For the external accesses under the conditions of 2 above, the problems can be avoided in the
following way:
1. Detection of DREQ edges: During the bus cycle, input a DREQ edge (rising edge) only once at
most.
2. When overrun-0 in DREQ level detection is specified: During the bus cycle, negate the DREQ
input after detection of the first DACK output negation but before the second DACK output
negation takes place.
3. When overrun-1 in DREQ level detection is specified: During the bus cycle, negate the DREQ
input after detection of the first DACK output assertion but before the second DACK output
assertion takes place.
Rev. 3.00 Jan. 18, 2008 Page 449 of 1458
REJ09B0033-0300