SH7720 Datasheet, PDF (673/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Bit Bit Name Initial Value R/W
2
TFRST
0
R/W
1
RFRST
0
R/W
0
LOOP
0
R/W
Description
Transmit FIFO Data Register Reset
Cancels the transmit data in the transmit FIFO data
register and resets the data to the empty state.
0: Disables reset operation*
1: Enables reset operation
Note: * The reset is executed in a power-on
reset or a manual reset.
Receive FIFO Data Register Reset
Cancels the receive data in the receive FIFO data
register and resets the data to the empty state.
0: Disables reset operation*
1: Enables reset operation
Note: * The reset is executed in a power-on
reset or a manual reset.
Loop Back Test
Internally connects the transmit output pin (TxD)
and receive input pin (RxD) and enables the loop
back test.
0: Disables the loop back test
1: Enables the loop back test
Rev. 3.00 Jan. 18, 2008 Page 611 of 1458
REJ09B0033-0300