SH7720 Datasheet, PDF (134/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
Table 2.9 Shift Instructions
Instruction
Instruction Code Operation
Privileged
Mode
Cycles
ROTL
Rn
0100nnnn00000100 T←Rn←MSB
–
1
ROTR Rn
0100nnnn00000101 LSB→Rn→T
–
1
ROTCL Rn
0100nnnn00100100 T←Rn←T
–
1
ROTCR Rn
0100nnnn00100101 T→Rn→T
–
1
SHAD
Rm, Rn 0100nnnnmmmm1100 Rn ≥ 0: Rn << Rm → Rn
–
1
Rn < 0: Rn >> Rm → [MSB → Rn]
SHAL
Rn
0100nnnn00100000 T←Rn←0
–
1
SHAR Rn
0100nnnn00100001 MSB→Rn→T
–
1
SHLD
Rm, Rn 0100nnnnmmmm1101 Rm ≥ 0: Rn << Rm → Rn
–
1
Rm < 0: Rn >> Rm → [0 → Rn]
SHLL
Rn
0100nnnn00000000 T←Rn←0
–
1
SHLR
Rn
0100nnnn00000001 0→Rn→T
–
1
SHLL2 Rn
0100nnnn00001000 Rn<<2 → Rn
–
1
SHLR2 Rn
0100nnnn00001001 Rn>>2 → Rn
–
1
SHLL8 Rn
0100nnnn00011000 Rn<<8 → Rn
–
1
SHLR8 Rn
0100nnnn00011001 Rn>>8 → Rn
–
1
SHLL16 Rn
0100nnnn00101000 Rn<<16 → Rn
–
1
SHLR16 Rn
0100nnnn00101001 Rn>>16 → Rn
–
1
T Bit
MSB
LSB
MSB
LSB
–
MSB
LSB
–
MSB
LSB
–
–
–
–
–
–
Rev. 3.00 Jan. 18, 2008 Page 72 of 1458
REJ09B0033-0300