SH7720 Datasheet, PDF (285/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 7 Exception Handling
A DMA error is not accepted and is retained if the BL bit is set to 1 and accepted when the BL bit
is cleared to 0. User break requests generated while the BL bit is set are ignored and are not
retained. Accordingly, user breaks are not accepted even if the BL bit is cleared to 0.
If a general exception other than a DMA address error or user break occurs while the BL bit is set
to 1, the CPU enters a state similar to that in effect immediately after a reset, and passes control to
the reset vector (H'A0000000) (multiple exception). In this case, unlike a normal reset, modules
other than the CPU are not initialized, the contents of EXPEVT, SPC, and SSR are undefined, and
this status is not detected by an external device.
To enable acceptance of multiple exceptions, the contents of SPC and SSR must be saved while
the BL bit is set to 1 after an exception has been accepted, and then the BL bit must be cleared to
0. Before restoring the SPC and SSR, the BL bit must be set to 1.
7.2.5 Exception Source Acceptance Timing and Priority
(1) Exception Request of Instruction Synchronous Type and Instruction Asynchronous
Type
Resets and interrupts are requested asynchronously regardless of the program flow. In general
exceptions, a DMA address error and a user break under the specific condition are also requested
asynchronously. The user cannot expect on which instruction an exception is requested. For
general exceptions other than a DMA address error and a user break under a specific condition,
each general exception corresponds to a specific instruction.
(2) Re-execution Type and Processing-completion Type Exceptions
All exceptions are classified into two types: a re-execution type and a processing-completion type.
If a re-execution type exception is accepted, the current instruction executed when the exception is
accepted is terminated and the instruction address is saved to the SPC. After returning from the
exception processing, program execution resumes from the instruction where the exception was
accepted. In a processing-completion type exception, the current instruction executed when the
exception is accepted is completed, the next instruction address is saved to the SPC, and then the
exception processing is executed.
During a delayed branch instruction and delay slot, the following operations are executed. A re-
execution type exception detected in a delay slot is accepted before executing the delayed branch
instruction. A processing-completion type exception detected in a delayed branch instruction or a
delay slot is accepted when the delayed branch instruction has been executed. In this case, the
acceptance of delayed branch instruction or a delay slot precedes the execution of the branch
destination instruction. In the above description, a delay slot indicates an instruction following an
Rev. 3.00 Jan. 18, 2008 Page 223 of 1458
REJ09B0033-0300