SH7720 Datasheet, PDF (53/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Tables
Section 1 Overview
Table 1.1 SH7720/SH7721 Features......................................................................................... 2
Table 1.2 Product Lineup (SH7720 Group).............................................................................. 8
Table 1.3 Product Lineup (SH7721 Group).............................................................................. 9
Table 1.4 List of Pin Assignments .......................................................................................... 13
Table 1.5 SH7720/SH7721 Pin Functions .............................................................................. 25
Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Virtual Address Space............................................................................................. 40
Register Initial Values............................................................................................. 43
Addressing Modes and Effective Addresses for CPU Instructions......................... 56
CPU Instruction Formats ........................................................................................ 60
CPU Instruction Types............................................................................................ 63
Data Transfer Instructions....................................................................................... 67
Arithmetic Operation Instructions .......................................................................... 69
Logic Operation Instructions .................................................................................. 71
Shift Instructions..................................................................................................... 72
Branch Instructions ................................................................................................. 73
System Control Instructions.................................................................................... 74
Operation Code Map............................................................................................... 77
Section 3 DSP Operating Unit
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Table 3.10
Table 3.11
Table 3.12
Table 3.13
Table 3.14
Table 3.15
CPU Processing Modes .......................................................................................... 83
Virtual Address Space............................................................................................. 84
Operation of SR Bits in Each Processing Mode ..................................................... 87
RS and RE Setting Rule.......................................................................................... 93
Repeat Control Instructions .................................................................................... 93
Repeat Control Macros ........................................................................................... 94
DSP Mode Extended System Control Instructions ................................................. 96
PC Value during Repeat Control (When RC[11:0] ≥ 2) ......................................... 99
Extended System Control Instructions in DSP Mode ........................................... 103
Overview of Data Transfer Instructions................................................................ 106
Modulo Addressing Control Instructions.............................................................. 108
Double Data Transfer Instruction Formats ........................................................... 111
Single Data Transfer Instruction Formats ............................................................. 112
Destination Register in DSP Instructions.............................................................. 114
Source Register in DSP Operations ...................................................................... 115
Rev. 3.00 Jan. 18, 2008 Page liii of lxii