SH7720 Datasheet, PDF (548/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Power-Down Modes
13.3.5 Standby Control Register 5 (STBCR5)
STBCR5 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Initial
Bit
Bit Name Value R/W Description
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
MSTP56 0
R/W Module Stop Bit 56
When the MSTP56 bit is set to 1, the supply of the clock
to the SDHI is halted.
0: Clock supply to SDHI halted
1: SDHI operates
Note: On the models not having the SDHI, this bit is
reserved and is always read as 0. The write value
should always be 0.
5

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
4
MSTP54 0
R/W Module Stop Bit 54
When the MSTP54 bit is set to 1, the supply of the clock
to the TPU is halted.
0: TPU operates
1: Clock supply to TPU halted
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 486 of 1458
REJ09B0033-0300