SH7720 Datasheet, PDF (387/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
9.4.4 SDRAM Control Register (SDCR)
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
Initial
Bit
Bit Name Value
31 to 21 
All 0
20
A2ROW1 0
19
A2ROW0 0
18

0
17
A2COL1 0
16
A2COL0 0
15, 14 
All 0
13
DEEP 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Number of Bits of Row Address for Area 2
R/W Specify the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
R Reserved
This bit is always read as 0. The write value should always
be 0.
R/W Number of Bits of Column Address for Area 2
R/W Specify the number of bits of column address for area 2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Deep Power-Down Mode
This bit is valid for low-power SDRAM. If the RMODE bit is
set to 1 while this bit is set to 1, the deep power-down entry
command is issued and the low-power SDRAM enters the
deep power-down mode.
0: Self-refresh mode
1: Deep power-down mode
Rev. 3.00 Jan. 18, 2008 Page 325 of 1458
REJ09B0033-0300