SH7720 Datasheet, PDF (761/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.8 Interrupt Enable Register (SIIER)
SIIER is a 16-bit readable/writable register that enables the issue of SIOF interrupts. When each
bit in this register is set to 1 and the corresponding bit in SISTR is set to 1, the SIOF issues an
interrupt.
Initial
Bit
Bit Name Value R/W Description
15
TDMAE 0
R/W Transmit Data DMA Transfer Request Enable
Transmits an interrupt as an interrupt to the CPU/DMA
transfer request. The TDREQE bit can be set as transmit
interrupts.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
14
TCRDYE 0
R/W Transmit Control Data Ready Enable
0: Disables interrupts due to transmit control data ready
1: Enables interrupts due to transmit control data ready
13
TFEMPE 0
R/W Transmit FIFO Empty Enable
0: Disables interrupts due to transmit FIFO empty
1: Enables interrupts due to transmit FIFO empty
12
TDREQE 0
R/W Transmit Data Transfer Request Enable
0: Disables interrupts due to transmit data transfer
requests
1: Enables interrupts due to transmit data transfer
requests
11
RDMAE 0
R/W Receive Data DMA Transfer Request Enable
Transmits an interrupt as an interrupt to the CPU/DMA
transfer request. The RDREQE bit can be set as receive
interrupts.
0: Used as a CPU interrupt
1: Used as a DMA transfer request to the DMAC
10
RCRDYE 0
R/W Receive Control Data Ready Enable
0: Disables interrupts due to receive control data ready
1: Enables interrupts due to receive control data ready
Rev. 3.00 Jan. 18, 2008 Page 699 of 1458
REJ09B0033-0300