SH7720 Datasheet, PDF (890/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 USB Function Controller (USBF)
25.3.33 Endpoint Stall Register 1 (EPSTL1)
EPSTL stalls each endpoint. The endpoint in which the stall bit is set to 1 returns a stall handshake
to the host from the next transfer when 1 is written to. For detailed operation, see section 25.8,
Stall Operations.
Bit Bit Name
7 to 2 
1
EP5 STL
0
EP4 STL
Initial Value R/W
All 0
R
0
R/W
0
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
EP5 Stall
Sets EP5 stall
EP4 Stall
Sets EP4 stall
25.3.34 Configuration Value Register (CVR)
CVR is a register to store the Configuration/Interface/ value to be set when the Set
Configuration/Set Interface command is normally received.
Bit Bit Name
7
CNFV1
6
CNFV0
5
INTV1
4
INTV0
3

Initial Value R/W Description
0
R Configuration Value
0
R The configuration setting value is stored when the Set
Configuration command has been received.
CNFV is updated when the SETC bit in the interrupt
flag register is set to 1.
0
R Interface Value
0
R The interface setting value is stored when the Set
Interface command has been received.
INTV is updated when the SETI bit in the interrupt flag
register is set to 1.
0
R Reserved
This bit is always read as 0.
Rev. 3.00 Jan. 18, 2008 Page 828 of 1458
REJ09B0033-0300